As this type of electronic component, a chip-type common-mode choke coil is disclosed, for example, in Patent Document 1. A common-mode choke coil is mounted to eliminate noise from a high-speed differential transmission line, and serves to efficiently transmit a differential signal in a normal mode and to eliminate invading noise in a common mode.
With recent size reduction and increases in density of electronic circuits, there has been a demand to minimize this chip-type common mode choke coil. However, minimization of the electronic component forcibly reduces the distance between outer electrodes, and this causes a stray capacitance between the outer electrodes. This stray capacitance may cause mismatching of the characteristic impedance near the outer electrodes. Mismatching of the characteristic impedance not only deteriorates the differential-signal transmission characteristic in a normal mode, but also changes the differential signal to common-mode noise. In order to overcome these problems, it is conceivable to reduce the width of the outer electrodes themselves. However, this reduces the fixing strength of the outer electrodes to a substrate.
For example, Patent Document 2 discloses a technique of suppressing a stray capacitance produced between outer electrodes by placing dielectric materials having a low dielectric constant under the outer electrodes. It is conceivable to apply this technique to an electronic component, such as a common-mode choke coil, in which a plurality of outer electrodes are adjacent at an end of a chip body.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 2000-277335
Patent Document 2: Japanese Unexamined Patent Application Publication No. H08-083734
Unfortunately, when the above-described technique disclosed in Patent Document 2 is applied to an electronic component such as a common-mode choke coil, the following problem is caused.
FIG. 14 is a schematic partial sectional view explaining the problem of the conventional art.
Through the use of the above-described technique, an effect of suppressing a stray capacitance is sufficiently achieved between opposing outer electrodes provided at both ends of a chip body. However, in this technique, low-constant dielectrics 111 and 112 are juxtaposed at one end of a chip body 100 having a high dielectric constant, and outer electrodes 101 and 102 are provided such as to cover the low-constant dielectrics 111 and 112, respectively, as shown in FIG. 14. For this reason, peripheral edge portions 101a and 102a of the low-constant dielectrics 111 and 112 are in contact with the chip body 100 having a high dielectric constant. Consequently, a capacitor is formed in which the peripheral edge portions 101a and 102a adjacent across the chip body 100 having a high dielectric constant serve as electrodes. As shown by broken lines in FIG. 14, a large stray capacitance C corresponding to the dielectric constant of the chip body 100 is produced between the peripheral edge portions 101a and 102a.